Session Chair: Mengjia Yan (Massachusetts Inst. of Technology)

Control Logic Synthesis: Drawing the Rest of the OWL
Zachary D. Sisco (University of California, Santa Barbara), Andrew David Alex (University of California, Santa Barbara), Zechen Ma (University of California, Santa Barbara), Yeganeh Aghamohammadi (University of California, Santa Barbara), Boming Kong (University of California, Santa Barbara), Benjamin Darnell (University of Illinois Urbana-Champaign), Timothy Sherwood (University of California, Santa Barbara), Ben Hardekopf (University of California, Santa Barbara), Jonathan Balkind (University of California, Santa Barbara)
Paper

CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS
Jiahui Xu (ETH Zurich), Lana Josipović (ETH Zurich)
Paper

AMuLeT: Automated Design-Time Testing of Secure Speculation Countermeasures
Bo Fu (University of Toronto), Leo Tenenbaum (University of Toronto), David Adler (University of Toronto), Assaf Klein (Technion - Israel Institute of Technology), Arpit Gogia (IMDEA Software Institute), Alaa R. Alameldeen (Simon Fraser University), Marco Guarnieri (IMDEA Software Institute), Mark Silberstein (Technion - Israel Institute of Technology), Oleksii Oleksenko (Azure Research, Microsoft), Gururaj Saileshwar (University of Toronto)
Paper

Don't Repeat Yourself! Coarse-Grained Circuit Deduplication to Accelerate RTL Simulation
Haoyuan Wang (UC Santa Cruz), Thomas Nijssen (UC Santa Cruz), Scott Beamer (UC Santa Cruz)
Paper

Parendi: Thousand-Way Parallel RTL Simulation
Mahyar Emami (EPFL), Thomas Bourgeat (EPFL), James R. Larus (EPFL)
Paper